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How to preserve the internal signal name in synthesis when using Cadence RTL compiler

rexnyu

Here is part of my script.

set_attribute write_vlog_preserve_net_name true

elaborate aes_fwd_top

ungroup -flatten -all

synthesize -to_mapped

write_hdl -mapped > aes_fwd_top-orig.v

But RTL compiler keeps changing my internal signal names with some random names in the verilog netlist file.

What is the proper way to use "write_vlog_preserve_net_name"? or I am using the wrong command.

  • Hmm....

    "Topic has 0 replies and 6091 views."

    Seems like there are a number of folks also having the same issue, yet "0" replies.

    You would think this might have made the  R&D priority list. 

    And  here we are three years later.

  • R&D does not monitor this forum. If a user has a serious issue, they need to contact support. This is a user forum, for users to help each other out with design issues and tool usage. Cadence employees (like myself) sometimes answer questions when they have time, but it is not a direct line to get immediate support. I wish more users were on this forum helping each other (as well as more Cadence employees).

  • Hi Jeff,

    as Kari pointed out, this is not a replacement for your support contact but a means for the community of ALL tool users to help each other out and share knowledge. You can be mad at the 6091 people that viewed it and provided no insight but it is no indication of R&D involvement. For all we know, the issue was addressed and the user never posted the conclusions.

    Lastly, please make sure you always post in the correct forum. Moderators do there best to re-assign but it is a human doing that after all so some can fall through the cracks from time to time. 

    gh-

  • The OP had the answer at the tip of his tongue, random names are by definition random.

    Only register instance names and top level port names are guaranteed to  remain consistent from synthesis run to run.

    Change anything ( attributes, RTL, constraints, libraries etc. etc. ) and synthesized combinational logic random names will flip to another 'synthesized' name.

    There are specialized tools and techniques "Conformal ECO" that map old to new names ,

    but those resources are reserved for experienced users that are already in really deep trouble.

    Or you could draw a schematic :  )

    Shawn

     

     

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