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How to preserve the internal signal name in synthesis when using Cadence RTL compiler

rexnyu

Here is part of my script.

set_attribute write_vlog_preserve_net_name true

elaborate aes_fwd_top

ungroup -flatten -all

synthesize -to_mapped

write_hdl -mapped > aes_fwd_top-orig.v

But RTL compiler keeps changing my internal signal names with some random names in the verilog netlist file.

What is the proper way to use "write_vlog_preserve_net_name"? or I am using the wrong command.

Parents

  • Hi Jeff,

    as Kari pointed out, this is not a replacement for your support contact but a means for the community of ALL tool users to help each other out and share knowledge. You can be mad at the 6091 people that viewed it and provided no insight but it is no indication of R&D involvement. For all we know, the issue was addressed and the user never posted the conclusions.

    Lastly, please make sure you always post in the correct forum. Moderators do there best to re-assign but it is a human doing that after all so some can fall through the cracks from time to time. 

    gh-

Reply

  • Hi Jeff,

    as Kari pointed out, this is not a replacement for your support contact but a means for the community of ALL tool users to help each other out and share knowledge. You can be mad at the 6091 people that viewed it and provided no insight but it is no indication of R&D involvement. For all we know, the issue was addressed and the user never posted the conclusions.

    Lastly, please make sure you always post in the correct forum. Moderators do there best to re-assign but it is a human doing that after all so some can fall through the cracks from time to time. 

    gh-

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