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How to preserve the internal signal name in synthesis when using Cadence RTL compiler

rexnyu

Here is part of my script.

set_attribute write_vlog_preserve_net_name true

elaborate aes_fwd_top

ungroup -flatten -all

synthesize -to_mapped

write_hdl -mapped > aes_fwd_top-orig.v

But RTL compiler keeps changing my internal signal names with some random names in the verilog netlist file.

What is the proper way to use "write_vlog_preserve_net_name"? or I am using the wrong command.

Parents

  • The OP had the answer at the tip of his tongue, random names are by definition random.

    Only register instance names and top level port names are guaranteed to  remain consistent from synthesis run to run.

    Change anything ( attributes, RTL, constraints, libraries etc. etc. ) and synthesized combinational logic random names will flip to another 'synthesized' name.

    There are specialized tools and techniques "Conformal ECO" that map old to new names ,

    but those resources are reserved for experienced users that are already in really deep trouble.

    Or you could draw a schematic :  )

    Shawn

     

     

Reply

  • The OP had the answer at the tip of his tongue, random names are by definition random.

    Only register instance names and top level port names are guaranteed to  remain consistent from synthesis run to run.

    Change anything ( attributes, RTL, constraints, libraries etc. etc. ) and synthesized combinational logic random names will flip to another 'synthesized' name.

    There are specialized tools and techniques "Conformal ECO" that map old to new names ,

    but those resources are reserved for experienced users that are already in really deep trouble.

    Or you could draw a schematic :  )

    Shawn

     

     

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