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RTL compiler to minimize area

Hamzah

Hello all,

 

I am using RTL compiler to synthesize a pure combiniational digital designs. I would like to know how to constraints the synthesis tool to minimize the Area as its first periority or even may be the only periority.

 

The shell script I use to synthesis my designs is:

#/bin/sh

SYN_ID=$2

FILE=$1

SYN_TOOL=rc

RC_REPORT=/tmp/syn.$SYN_ID.rpt

AREA=/tmp/syn.$SYN_ID.area

$SYN_TOOL > $RC_REPORT << EOF

set_attribute lib_search_path ../../../Digital_Standard_Cell_Library/synopsys/models

set_attribute library {saed90nm_typ.lib}

read_hdl $FILE

set_attribute avoid true LNANDX1 LNANDX2

elaborate

synthesize -to_generic

synthesize -to_mapped

synthesize -to_mapped

synthesize -to_mapped

synthesize -to_mapped

synthesize -to_mapped -effort high

write_hdl -mapped > /tmp/syn.$SYN_ID.v

echo [get_attribute area /designs/*]> $AREA

quit

EOF

 How can I constraint the RC to minimize the area as much as possible?

Alos, I have some designs that desribes in truth tables format (Berkeley PLA format), How can I read these designs with cadence?

 

Thanks a lot. 

Parents

  • glennramalho,

     RTL-Compiler does not accept a max_area constraint because the tool's philosophy is to always synthesize to the minimum area necessary to meet your other goals (timing and power).  Lower area is pointless if you cannot meet timing.  And, why would anyone want more area than necessary?  With those thoughts in mind, an area constraint doesn't really make sense.

     As gh said, the best way to reduce area is to relax your timing constraints, or at least to ensure you are not over-constraining.  RTL-Compiler's core engines are much different than DC's.  RC analyzes all paths before mapping, and it maps timing critical paths differently from non-critical paths.  It structures datapath differently depending on whether the paths are critical or not.  Etc.  So, RC's results are sensitive to timing constraints.  Try not to over-constrain.

     That being said, there are multiple things that can cause larger than necessary area.  Check that these are not occurring:

    • excessive Design Rule constraints (max cap, max fanout, max transition)
    • turning off boundary optimization, which prevents constant propagation
    • disabling sequental optimization

    There are also things you can try to reduce area.  

    • enable clock gating (sequential feedback muxes are replaced by clock gaters, which can reduce area)
    • enable sequential merging

    Neither of the above lists should be considered complete.  It is just what I thought of off the top of my head.

     

     

Reply

  • glennramalho,

     RTL-Compiler does not accept a max_area constraint because the tool's philosophy is to always synthesize to the minimum area necessary to meet your other goals (timing and power).  Lower area is pointless if you cannot meet timing.  And, why would anyone want more area than necessary?  With those thoughts in mind, an area constraint doesn't really make sense.

     As gh said, the best way to reduce area is to relax your timing constraints, or at least to ensure you are not over-constraining.  RTL-Compiler's core engines are much different than DC's.  RC analyzes all paths before mapping, and it maps timing critical paths differently from non-critical paths.  It structures datapath differently depending on whether the paths are critical or not.  Etc.  So, RC's results are sensitive to timing constraints.  Try not to over-constrain.

     That being said, there are multiple things that can cause larger than necessary area.  Check that these are not occurring:

    • excessive Design Rule constraints (max cap, max fanout, max transition)
    • turning off boundary optimization, which prevents constant propagation
    • disabling sequental optimization

    There are also things you can try to reduce area.  

    • enable clock gating (sequential feedback muxes are replaced by clock gaters, which can reduce area)
    • enable sequential merging

    Neither of the above lists should be considered complete.  It is just what I thought of off the top of my head.

     

     

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