RTL compiler to minimize area

Hi Hamza,

 if area is all you care about, then you may as well not read any timing constraints. RC always reclaims area since the assumption is no user want there design to be bigger than it needs to be :)

 I noticed your flow does full mapping 5 times. Doing that even once an getting any meaningful improvement to area would be considered a bug. It is either unnecessary, a bug, or you are running an old version of the tools. A question I always ask is, do you expect the design to be smaller than it already is. Unfortunately, wanting it to be smaller is not enought to make it smaller...

  As per Berkley PLA format, I do not have an answer for you altough I seem to recall a similar question a few years back in some EDA forum. A quick search may yield you some results

 gh-

Is there no way to focus on Area on Cadence?

I have worked more with Synopsys and the tool does not do it very well, it automatically tries to synthesize for speed no matter what you do. There you can ease it a bit by making relaxed timing constraints and use the "set_max_area 0" command. Then you do a "set_max_area" to 10% less than the result and do an incremental synthesis and squeeze a bit more. That is Synopsys though, not Cadence. Cadence does not support the set_max_area command.

 Back to the combinatorial code though, you might want to be careful as these synthesis tools should not have too much freedom. The quality can drop quite a bit when you have no constraint at all. The rule at work then was to just put some constraint in to force the tool to do some effort as it stops as soon as all constraints are matched.

glennramalho,

 RTL-Compiler does not accept a max_area constraint because the tool's philosophy is to always synthesize to the minimum area necessary to meet your other goals (timing and power).  Lower area is pointless if you cannot meet timing.  And, why would anyone want more area than necessary?  With those thoughts in mind, an area constraint doesn't really make sense.

 As gh said, the best way to reduce area is to relax your timing constraints, or at least to ensure you are not over-constraining.  RTL-Compiler's core engines are much different than DC's.  RC analyzes all paths before mapping, and it maps timing critical paths differently from non-critical paths.  It structures datapath differently depending on whether the paths are critical or not.  Etc.  So, RC's results are sensitive to timing constraints.  Try not to over-constrain.

 That being said, there are multiple things that can cause larger than necessary area.  Check that these are not occurring:

• excessive Design Rule constraints (max cap, max fanout, max transition)
• turning off boundary optimization, which prevents constant propagation
• disabling sequental optimization

There are also things you can try to reduce area.  

• enable clock gating (sequential feedback muxes are replaced by clock gaters, which can reduce area)
• enable sequential merging

Neither of the above lists should be considered complete.  It is just what I thought of off the top of my head.

Hey Guys, Thank you for your help.

gh, when I do multiple mapping, the synthesis result is different I don't know why. sometimes, the area geos form 630 to 570. and sometime if you make more mapping the area goes up again. !!

I used to run DC before I switch to RC. DC has a better performance in terms of Area optimization. I guess one of the main reason of that, DC accepts the PLA format (tabular format) which allow me to put some Don't care sets of my design. This gives DC a relaxation space to get more optimized design in terms of Area, power, and Delay.

Also, Do i need to put any delay constraints for my computational circuits in my script shown above to get better area performance??

By the way, I added these constraints to the above script: set_attribute dp_area_mode true / set incremental_opto 0 in addition to these, I don't know if they are valid or not :) They are just a guess. :) set global_area 1 set max_area 0 set area_down 1

Thanks a lot.

Hamzah