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RTL compiler to minimize area

Hamzah

Hello all,

 

I am using RTL compiler to synthesize a pure combiniational digital designs. I would like to know how to constraints the synthesis tool to minimize the Area as its first periority or even may be the only periority.

 

The shell script I use to synthesis my designs is:

#/bin/sh

SYN_ID=$2

FILE=$1

SYN_TOOL=rc

RC_REPORT=/tmp/syn.$SYN_ID.rpt

AREA=/tmp/syn.$SYN_ID.area

$SYN_TOOL > $RC_REPORT << EOF

set_attribute lib_search_path ../../../Digital_Standard_Cell_Library/synopsys/models

set_attribute library {saed90nm_typ.lib}

read_hdl $FILE

set_attribute avoid true LNANDX1 LNANDX2

elaborate

synthesize -to_generic

synthesize -to_mapped

synthesize -to_mapped

synthesize -to_mapped

synthesize -to_mapped

synthesize -to_mapped -effort high

write_hdl -mapped > /tmp/syn.$SYN_ID.v

echo [get_attribute area /designs/*]> $AREA

quit

EOF

 How can I constraint the RC to minimize the area as much as possible?

Alos, I have some designs that desribes in truth tables format (Berkeley PLA format), How can I read these designs with cadence?

 

Thanks a lot. 

Parents

  • Hey Guys, Thank you for your help.

    gh, when I do multiple mapping, the synthesis result is different I don't know why. sometimes, the area geos form 630 to 570. and sometime if you make more mapping the area goes up again. !!

    I used to run DC before I switch to RC. DC has a better performance in terms of Area optimization. I guess one of the main reason of that, DC accepts the PLA format (tabular format) which allow me to put some Don't care sets of my design. This gives DC a relaxation space to get more optimized design in terms of Area, power, and Delay.

     

    Also, Do i need to put any delay constraints for my computational circuits in my script shown above to get better area performance??

    By the way, I added these constraints to the above script: set_attribute dp_area_mode true / set incremental_opto 0 in addition to these, I don't know if they are valid or not :) They are just a guess. :) set global_area 1 set max_area 0 set area_down 1

     

     

    Thanks a lot.

    Hamzah 

Reply

  • Hey Guys, Thank you for your help.

    gh, when I do multiple mapping, the synthesis result is different I don't know why. sometimes, the area geos form 630 to 570. and sometime if you make more mapping the area goes up again. !!

    I used to run DC before I switch to RC. DC has a better performance in terms of Area optimization. I guess one of the main reason of that, DC accepts the PLA format (tabular format) which allow me to put some Don't care sets of my design. This gives DC a relaxation space to get more optimized design in terms of Area, power, and Delay.

     

    Also, Do i need to put any delay constraints for my computational circuits in my script shown above to get better area performance??

    By the way, I added these constraints to the above script: set_attribute dp_area_mode true / set incremental_opto 0 in addition to these, I don't know if they are valid or not :) They are just a guess. :) set global_area 1 set max_area 0 set area_down 1

     

     

    Thanks a lot.

    Hamzah 

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