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using ModelSim/QuestaSim VCD file in RTL compiler

dkhan

Hi,

I want to use VCD file from QuestaSim 6.0 in RTL compiler to obtain power report. The netlist file I am using in QuestaSim for simulation and VCD file generation is also generated by RTL compiler byt when I run following commands I got no asserted signals in the power result. Does RTL compiler supports other VCD files besides from NCVHDL?

read_netlist synthesized_RISC_32.v

define_clock -name clk_main -period 5000 [find / -port clk_main]

read_vcd -module RISC_32 -static RISC_32.vcd

report power

Parents

  •  Hi dkhan,

     

    VCD is VCD and it does not matter what tool generates it as long as VCD it is legal. You will have to do some additional debug and figure why it is not annotating. Most common reason is testbench generating VCD scoped at the testbench level which the design obviously does not have. Other reasons are naming conventions on elaborated flops, etc.

     As I said, a quick peek at why your annotation is failing will shed ample light on your issue

    gh-

Reply

  •  Hi dkhan,

     

    VCD is VCD and it does not matter what tool generates it as long as VCD it is legal. You will have to do some additional debug and figure why it is not annotating. Most common reason is testbench generating VCD scoped at the testbench level which the design obviously does not have. Other reasons are naming conventions on elaborated flops, etc.

     As I said, a quick peek at why your annotation is failing will shed ample light on your issue

    gh-

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