I want to use VCD file from QuestaSim 6.0 in RTL compiler to obtain power report. The netlist file I am using in QuestaSim for simulation and VCD file generation is also generated by RTL compiler byt when I run following commands I got no asserted signals in the power result. Does RTL compiler supports other VCD files besides from NCVHDL?
read_netlist synthesized_RISC_32.vdefine_clock -name clk_main -period 5000 [find / -port clk_main]read_vcd -module RISC_32 -static RISC_32.vcd
VCD is VCD and it does not matter what tool generates it as long as VCD it is legal. You will have to do some additional debug and figure why it is not annotating. Most common reason is testbench generating VCD scoped at the testbench level which the design obviously does not have. Other reasons are naming conventions on elaborated flops, etc.
As I said, a quick peek at why your annotation is failing will shed ample light on your issue
Yes I have checked the contents of VCD file and it only contains signals from the component I am testing. However when I convert this VCD file into saif format using vcd2saif tool from Synopsys it reads correctly in RTL compiler.
It is great that you got it to work with vcd2saif.
However, that should not be necessary. I suspect you need to use the -vcd_scope (or -vcd_module in older releases) option to read_vcd in order to select the "scope" in the VCD that you want to apply to the top design in RC.
It is very common for a VCD to only contain signals from the design you are interested in, but also contain the full hierarchy from the testbench. For example, your VCD may look like this:
$scope module tb $end$scope module dut $end$scope module my_top_design $end$var wire 1 Tc4# clk $end$var wire 1 Eb4# reset_n $end....
In this above case, you need to specify "read_vcd -vcd_scope tb/dut/my_top_design ..." or just "read_vcd -vcd_scope my_top_design ...".