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using ModelSim/QuestaSim VCD file in RTL compiler

dkhan

Hi,

I want to use VCD file from QuestaSim 6.0 in RTL compiler to obtain power report. The netlist file I am using in QuestaSim for simulation and VCD file generation is also generated by RTL compiler byt when I run following commands I got no asserted signals in the power result. Does RTL compiler supports other VCD files besides from NCVHDL?

read_netlist synthesized_RISC_32.v

define_clock -name clk_main -period 5000 [find / -port clk_main]

read_vcd -module RISC_32 -static RISC_32.vcd

report power

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  •  Thanks gh.

     Yes I have checked the contents of VCD file and it only contains signals from the component I am testing. However when I convert this VCD file into saif format using vcd2saif tool from Synopsys it reads correctly in RTL compiler.     

     

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  •  Thanks gh.

     Yes I have checked the contents of VCD file and it only contains signals from the component I am testing. However when I convert this VCD file into saif format using vcd2saif tool from Synopsys it reads correctly in RTL compiler.     

     

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