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using ModelSim/QuestaSim VCD file in RTL compiler

dkhan

Hi,

I want to use VCD file from QuestaSim 6.0 in RTL compiler to obtain power report. The netlist file I am using in QuestaSim for simulation and VCD file generation is also generated by RTL compiler byt when I run following commands I got no asserted signals in the power result. Does RTL compiler supports other VCD files besides from NCVHDL?

read_netlist synthesized_RISC_32.v

define_clock -name clk_main -period 5000 [find / -port clk_main]

read_vcd -module RISC_32 -static RISC_32.vcd

report power

Parents

  •  It is great that you got it to work with vcd2saif.

     However, that should not be necessary.  I suspect you need to use the -vcd_scope (or -vcd_module in older releases) option to read_vcd in order to select the "scope" in the VCD that you want to apply to the top design in RC.

     It is very common for a VCD to only contain signals from the design you are interested in, but also contain the full hierarchy from the testbench.  For example, your VCD may look like this:

    $scope module tb $end

    $scope module dut $end

    $scope module my_top_design $end
    $var wire       1 Tc4# clk $end
    $var wire       1 Eb4# reset_n $end
    ....

     In this above case, you need to specify "read_vcd -vcd_scope tb/dut/my_top_design ..." or just "read_vcd -vcd_scope my_top_design ...".

  • in reply to bmiller

    Hi, 

    can anyone tell me how to check the asserted toggle rate and asserted probability in the genus (synthesis tool) 17.20 version.

    Following commands is showing error in running,

    get_db lp_asserted_toggle_rate

    get_db lp_asseted_probability

    Can anyone help me with this?

    Thanks 

Reply
  • in reply to bmiller

    Hi, 

    can anyone tell me how to check the asserted toggle rate and asserted probability in the genus (synthesis tool) 17.20 version.

    Following commands is showing error in running,

    get_db lp_asserted_toggle_rate

    get_db lp_asseted_probability

    Can anyone help me with this?

    Thanks 

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