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RC - read_hdl

Yemelya

Hi Everyone,

When reading verilog (read_hdl -sv), first file is common variable definitions (like `define and localparam). There is no problem loading this file, however when loading the actual RTL design it cannot recognize the mentioned above variables (Error - undeclared).

If the same  variable definitions file added to RTL as `include it works, but there are too many RTL files and I have no permission to modify them.

Any idea what could the issue with loading it by (read_hdl -sv)?

Thanks a lot!

Boris



Parents

  • Hi Grasshopper,

    Thanks a lot for your help. Actually script was reading all the files line by line with read_hdl for each one. I believed that if we define library it will resolve the scope visibility issue, but it didn't. 

    It works now, after I fixed it as you advised:

    read_hdl  { include.v a.v }
    read_hdl  { include.v b.v }
    read_hdl  { include.v c.v }

    Again, thank you very much for such a quick and useful response!

    -Yemelya



Reply

  • Hi Grasshopper,

    Thanks a lot for your help. Actually script was reading all the files line by line with read_hdl for each one. I believed that if we define library it will resolve the scope visibility issue, but it didn't. 

    It works now, after I fixed it as you advised:

    read_hdl  { include.v a.v }
    read_hdl  { include.v b.v }
    read_hdl  { include.v c.v }

    Again, thank you very much for such a quick and useful response!

    -Yemelya



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