We are doing a design which needs the multiplier. Does Cadence RTL compiler has the library which is same as Synopsys Designware?
Thanks for your reply. I also have an question. If I use A=op1*op2, I cannot control the circuit and the timing. For example, if the verilog code is
always @(posedge clk or negedge rst)
In this code, I hope the multiplication can be finished in one clock cycle. If it cannot be finished in one clock cycle, my max frequency of the circuit would be decreased. However, DW has many different kinds of multipliers. We can use the multiplier with higher frequency and of cource the area may be larger. But we can choose we prefer speed or the area.
Is my statement right? Actually I'm a newbie in VLSI design and I look forward to your reply.