• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Logic Design
  3. Question about the multiplier

Stats

  • Locked Locked
  • Replies 3
  • Subscribers 62
  • Views 15885
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Question about the multiplier

bravepanda
bravepanda over 12 years ago

Hello,

 

We are doing a design which needs the multiplier. Does Cadence RTL compiler has the library which is same as Synopsys Designware?

 

Thanks. 

  • Cancel
Parents
  • bravepanda
    bravepanda over 12 years ago

    Hi Grasshopper,

    Thanks for your reply. I also have an question. If I use A=op1*op2, I cannot control the circuit and the timing. For example, if the verilog code is

     always @(posedge clk or negedge rst)

    if (~rst)

    A <=0;

    else

    A<=op1*op2 ;

    In this code, I hope the multiplication can be finished in one clock cycle. If it cannot be finished in one  clock cycle, my max frequency of the circuit would be decreased. However, DW has many different kinds of multipliers. We can use the multiplier with higher frequency and of cource the area may be larger. But we can choose we prefer speed or the area. 

     Is my statement right? Actually I'm a newbie in VLSI design and I look forward to your reply.

     

    Regards

     

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • bravepanda
    bravepanda over 12 years ago

    Hi Grasshopper,

    Thanks for your reply. I also have an question. If I use A=op1*op2, I cannot control the circuit and the timing. For example, if the verilog code is

     always @(posedge clk or negedge rst)

    if (~rst)

    A <=0;

    else

    A<=op1*op2 ;

    In this code, I hope the multiplication can be finished in one clock cycle. If it cannot be finished in one  clock cycle, my max frequency of the circuit would be decreased. However, DW has many different kinds of multipliers. We can use the multiplier with higher frequency and of cource the area may be larger. But we can choose we prefer speed or the area. 

     Is my statement right? Actually I'm a newbie in VLSI design and I look forward to your reply.

     

    Regards

     

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information