We are doing a design which needs the multiplier. Does Cadence RTL compiler has the library which is same as Synopsys Designware?
RC suppors DW as well as its own chipware. That being said, best results are obtained using behavior code. In other words, coding with
A = op1 * op2
tends to produce better results than
Quick history is that DW was created to address synthesis shortcoming in handling of arithmetic and other functions. Since then, synthesis technology has come a long way
Last but not least, also note that not all DW is created equal. Whilte RC makes every effort to support the free set of DW libraries, several DW libraries are paid IP and unpublished by Synopsys hence not supported (i.e DW_pci..., etc.)
One more thing, the list of officially supported DW components can be found in the documentation under CW Reference Manual, Third Party Libraries. If you do not find the component you are using, please contact your AE and/or file an SR
Thanks for your reply. I also have an question. If I use A=op1*op2, I cannot control the circuit and the timing. For example, if the verilog code is
always @(posedge clk or negedge rst)
In this code, I hope the multiplication can be finished in one clock cycle. If it cannot be finished in one clock cycle, my max frequency of the circuit would be decreased. However, DW has many different kinds of multipliers. We can use the multiplier with higher frequency and of cource the area may be larger. But we can choose we prefer speed or the area.
Is my statement right? Actually I'm a newbie in VLSI design and I look forward to your reply.
if you have a construct
A = op1 * op2
your synthesis tool will infer the correct architecture given your timing / power / area requirements whether you use DW, CW, or anything else. There are some cases were DW component will also allow specifying the number of pipelining stages. However, it is still hard-coded in your designs so whether you hard-code 3 stages in DW or in HDL, the impact is the same