We are doing a design which needs the multiplier. Does Cadence RTL compiler has the library which is same as Synopsys Designware?
if you have a construct
A = op1 * op2
your synthesis tool will infer the correct architecture given your timing / power / area requirements whether you use DW, CW, or anything else. There are some cases were DW component will also allow specifying the number of pipelining stages. However, it is still hard-coded in your designs so whether you hard-code 3 stages in DW or in HDL, the impact is the same