I wont to generate a fixed delay, for which I have used multiple NOT gates and instantiated in the top design. While synthesizing, RTL compiler optimizes the gates added and put a direct net without delay. How to get such fixed delays synthesized??
I do not know what your HDL looks like but behavioral code for a chain of inverters would certainly be optimized. That is what synthesis tools are designed to do. You have several alternatives:
(1) hand instantiate in HDL and preserve/dont_touch(2) use 'edit_netlist ...' commandsto create the buffer/delay cell chain