Stats

Locked Locked
Replies 2
Subscribers 63
Views 13893
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

preserving a subdesign from optimization

I wont to generate a fixed delay, for which I have used multiple NOT gates and instantiated in the top design. While synthesizing, RTL compiler optimizes the gates added and put a direct net without delay. How to get such fixed delays synthesized??

aflex over 11 years ago

Speed-up IC Compiler placement by 1.5X. Also check the circuit congestion. This might help in fixing delays synthesized.
Cancel
Vote Up 0 Vote Down

Cancel
grasshopper over 11 years ago

I do not know what your HDL looks like but behavioral code for a chain of inverters would certainly be optimized. That is what synthesis tools are designed to do. You have several alternatives:
(1) hand instantiate in HDL and preserve/dont_touch
(2) use 'edit_netlist ...' commandsto create the buffer/delay cell chain
gh-
Cancel
Vote Up 0 Vote Down

Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.