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preserving a subdesign from optimization

I wont to generate a fixed delay, for which I have used multiple NOT gates and instantiated in the top design. While synthesizing, RTL compiler optimizes the gates added and put a direct net without delay. How to get such fixed delays synthesized??

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aflex over 11 years ago

Speed-up IC Compiler placement by 1.5X. Also check the circuit congestion. This might help in fixing delays synthesized.
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aflex over 11 years ago

Speed-up IC Compiler placement by 1.5X. Also check the circuit congestion. This might help in fixing delays synthesized.
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