Stats

Locked Locked
Replies 2
Subscribers 63
Views 14022
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

RC compiler and ports consisting of arrays of vectors

Hello,

I've a design written in VHDL which has a port (e.g. called "test") defined as array of vectors.

During the elaboration within RC, this port is splitted up into "\test[0]", "\test[1]", ... which makes problems in the post synthesis simulation.

Is there a possibility to prevent this behaviour?
I've already tried to use "set_attr array_naming_style" and similar commands, but this does not help. Additionally I would like to pevent to use a mapper for the post synthesis simulation.

Thank you very much!

Best regards,
Markus

Parents

olalivier over 7 years ago

Hi Markusk,

did you find the solution to this problem ? I'm facing the exact same issue.

Olivier
Cancel
Vote Up 0 Vote Down

Cancel

Reply

olalivier over 7 years ago

Hi Markusk,

did you find the solution to this problem ? I'm facing the exact same issue.

Olivier
Cancel
Vote Up 0 Vote Down

Cancel

Children

MarkusK over 7 years ago in reply to olalivier

Hello Olivier,

not really, I did some work around like building a wrapper so I was able to reuse the original test case setup. Depending on the array size this can be an ugly job...

Best regards,
Markus
Cancel
Vote Up 0 Vote Down

Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.