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How to handle rtl-instantiated low power cells?

TriStated

While using IEEE1801 standard for power intent in synthesis with RTL compiler, how does one handle the RTL - instantiated low power cells? The tool is not honoring the hand instantiated cells and is inserting low power cells again. 

Thanks in advance.

Parents
  • You will need to run the command clock_gating import for the tool to recognize them if you do not want fine-gating. Keep in mind that depending on toggle of signals, there is a purpose to multi-level gating so you may or may not want it depending on design needs and behavior
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  • You will need to run the command clock_gating import for the tool to recognize them if you do not want fine-gating. Keep in mind that depending on toggle of signals, there is a purpose to multi-level gating so you may or may not want it depending on design needs and behavior
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