Genus synthesis | SystemVerilog in-code attribute assignment

Hi,

I’m trying to determine whether Cadence Genus supports SystemVerilog in-code synthesis attributes (similar to how Vivado does), for example:
(* dont_touch = "true" *) logic mysignal;
My goal is to simplify my timing.sdc file.

When I try this, Genus reports:
Warning : Unused attribute [VLOGPT-506]

I’ve tested several variations without success and haven’t found much documentation or examples for Genus specifically.
- Does Genus actually support this style of attribute assignment?
- If so, what is the correct syntax?
- Can it be applied to module instances, ports, registers, or nets?

Any insights would be greatly appreciated.

Thanks in advance,
Siebe