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Timing closure on cloned clock gate enable inputs

YJ202602057834

Our IP has a software controlled clock gate controlling an entire clock domain (several hundred flops). I noticed that in some cases, the clock gate is cloned post CTS, which create a large fanout path from the enable to the different clones. This path fails then fails timing checks. Apologies if this should not come as a surprise; I'm mostly a Verilog guy.

I have searched quite a lot online but could not find a reliable method of dealing with this kind of problem. The only method that could seemingly solve this is a set_max_fanout/set_register_duplication directive on the enable flop, but for reasons that people online do not explain, backend engineers do not like to use these directives. So:

  1. Is there an industry-standard way to deal with this kind of problems? 
  2. Can anyone tell me why set_max_fanout/set_register_duplication directives are frowned upon?

I have some ideas regarding 1 but they usually involve severe limits on the users to configure clock gating only within a reset context.

Many thanks in advance!

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  • YJ202504163215

    You may want to clone the clock gates during synthesis itself. There you can clone the enable flop as well. That way you see this issue much earlier than waiting until post cts.

    Another solution if for any reason it is not duplicated during synthesis you can try to duplicate during prects that is during place_opt_design. You can clone enable flop post syn thesis but it tends to be not on the expected lines. The issue is the logic on the data path is dependent on too many inputs and using the above commands you may have to clone path from all the inputs to allow you to move the combinational cells freely. The tendency of the tool is to place clock gates closer to fanout flops thereby keeping latency on the lower side but the impact is seen on the enable side.

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  • YJ202504163215

    You may want to clone the clock gates during synthesis itself. There you can clone the enable flop as well. That way you see this issue much earlier than waiting until post cts.

    Another solution if for any reason it is not duplicated during synthesis you can try to duplicate during prects that is during place_opt_design. You can clone enable flop post syn thesis but it tends to be not on the expected lines. The issue is the logic on the data path is dependent on too many inputs and using the above commands you may have to clone path from all the inputs to allow you to move the combinational cells freely. The tendency of the tool is to place clock gates closer to fanout flops thereby keeping latency on the lower side but the impact is seen on the enable side.

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