AMS Designer & Parameter Arrays

Markus,

Maybe it would help if you posted both the example VerilogAMS code and also the error you get to narrow down precisely what the problem you are seeing is?

Regards,

Andrew.

Hello Andrew,

you're right. It's much better with a short example and the exact error message:

 (Shorted) Code:

module my_module_v0(a);
inout [0:1] a;
electrical [0:1] a;
parameter real cap[0:5] = {0.0,0.0,0.0,0.0,0.0,0.0};
analog
begin
end

Error Message when starting an AMS simulation (MMSIM10 && NCSIM 10):

parameter real cap[0:5] = {0.0,0.0,0.0,0.0,0.0,0.0};
                           |   [[Comment: placed at first "[" ]]
ncvlog: *E,NOTSUP (/pathToFile/my_module_v0/veriloga/veriloga.va,63|18): In AMS Designer, parameter array declaration is not supported.

The tools are not at the most recent version, but according the documentation "parameter array declarations" are still not supported in NCSIM 12.

It is clear to me that parameter arrays in verilogAMS are supported only for "pure" Spectre simulations, but a AMS simulation would be very helpful (=much less simulation time) to verify the overall system. The question is how I might change the model in a simple way, so that I can run a AMS simulation (replacing the parameter by a constant is no option for me).

Thank you very much.

Best regards,

Markus

Markus,

I've done some checks, and this should (at last) be implemented in INCISIV13.1, which is due for release around June 23rd or so (I don't have the precise date). Might you be able to wait a month?

Regards,

Andrew.

Hello Andrew,

thank you very much!

For sure, we would like to run the simulation(s) as early as possible, but one month is a period that's acceptable :-)
I'll regulary check the release notes of Cadence then!

Best regards,
Markus