Stats

  • Locked Locked
  • Replies 4
  • Subscribers 64
  • Views 2165
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

AMS Designer & Parameter Arrays

MarkusK

Hello everybody,

I would like to run a mixed mode simulation using some VerilogAMS code. In this code I currently use some parameter arrays to hand over parameters. Unfortunately I get the message that parameter arrays are not supported during the netlisting.

The simpliest solution would be to split up the parameter arrays, but I do not want to do this.

Has anybody an idea how I might overcome this problem without rewritting all of the code?

Thank you very much,
Markus

Parents

  • Hello Andrew,

    you're right. It's much better with a short example and the exact error message:

     (Shorted) Code:

    module my_module_v0(a);
    inout [0:1] a;
    electrical [0:1] a;
    parameter real cap[0:5] = {0.0,0.0,0.0,0.0,0.0,0.0};
    analog
    begin
    end

    Error Message when starting an AMS simulation (MMSIM10 && NCSIM 10):

    parameter real cap[0:5] = {0.0,0.0,0.0,0.0,0.0,0.0};
                               |   [[Comment: placed at first "[" ]]
    ncvlog: *E,NOTSUP (/pathToFile/my_module_v0/veriloga/veriloga.va,63|18): In AMS Designer, parameter array declaration is not supported.

    The tools are not at the most recent version, but according the documentation "parameter array declarations" are still not supported in NCSIM 12.

    It is clear to me that parameter arrays in verilogAMS are supported only for "pure" Spectre simulations, but a AMS simulation would be very helpful (=much less simulation time) to verify the overall system. The question is how I might change the model in a simple way, so that I can run a AMS simulation (replacing the parameter by a constant is no option for me).

    Thank you very much.

    Best regards,

    Markus

Reply

  • Hello Andrew,

    you're right. It's much better with a short example and the exact error message:

     (Shorted) Code:

    module my_module_v0(a);
    inout [0:1] a;
    electrical [0:1] a;
    parameter real cap[0:5] = {0.0,0.0,0.0,0.0,0.0,0.0};
    analog
    begin
    end

    Error Message when starting an AMS simulation (MMSIM10 && NCSIM 10):

    parameter real cap[0:5] = {0.0,0.0,0.0,0.0,0.0,0.0};
                               |   [[Comment: placed at first "[" ]]
    ncvlog: *E,NOTSUP (/pathToFile/my_module_v0/veriloga/veriloga.va,63|18): In AMS Designer, parameter array declaration is not supported.

    The tools are not at the most recent version, but according the documentation "parameter array declarations" are still not supported in NCSIM 12.

    It is clear to me that parameter arrays in verilogAMS are supported only for "pure" Spectre simulations, but a AMS simulation would be very helpful (=much less simulation time) to verify the overall system. The question is how I might change the model in a simple way, so that I can run a AMS simulation (replacing the parameter by a constant is no option for me).

    Thank you very much.

    Best regards,

    Markus

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.