I need to model a verilog-ams bias current model.
I had coded in this way,
I(out) <+ 1uA.
In TB i put V(out) <+I(out)/R_LAOD.
This worked fine at module level.
Does this way of model works when the module connects with a SPICE block where the current is begin sinked.
Is this the correct way to model the bias current in verilog AMS.
Please provide your inputs to code the BIAS currents properly.
I don't think you've given enough details to go on, really. Please elaborate if you want an answer - I couldn't quite work out what you're asking (or even quite what you've implemented). Perhaps some pictures might help?
I have BIAS block and
BIAS sources 1uA
current and LDO sinks the same 1uA current.
I(bias) <+ 1e-6;
I(bias) <+ 0.0;
I(bias)*R_load; //If i do not limit the bias pin voltage,then V(bias) is going to much higher values which is not desirable.
&& I(bias)>0.8e-6) begin
V(ldo_out) <+ 1.8;
V(ldo_out) <+ 0.0;
Now I want to replace the LDO block with SPICE instead of v-ams.
In this case does the MOS in LDO block sinking the 1uA bias current limits the voltage of bias pin.
I see no reason why this should be an issue.
I haven't tried to replace it with SPICE because we are at initial phase of developing the VAMS Models.
Once i try it and will post my findings for any issues and concerns.