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Verilog-AMS Bias Current Modelling

shalem7

Hi All,

I need to model a verilog-ams bias current model.

I had coded in this way,

I(out) <+ 1uA.

In TB i put V(out) <+I(out)/R_LAOD.

This worked fine at module level.

Does this way of model works when the module connects with a SPICE block where the current is begin sinked.

Is this the correct way to model the bias current in verilog AMS.

Please provide your inputs to code the BIAS currents properly.

Thanks,

Shalem

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