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An Mixed-Sim(spectreverilog) Error: Component name (cdsNet0) not declared

Lynn Lou over 11 years ago

Dear All,

I am trapped by a spectreverilog error for sometime. I cannot do tran simulation, and in the output log, it says:

Error! Component name (cdsNet0) not declared [Verilog-CNNOD]

"saveDefs", 6: test.top.I0.cdsNet0

Could anyone help me out of this? Thank you in advance.

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Andrew Beckett over 11 years ago

From doing a bit of hunting around, I think this can happen if you use escaped names (e.g. \a ) in textual views.
But hard to be sure without seeing your data. Maybe you can contact customer support?
Regards,
Andrew.
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Andrew Beckett over 11 years ago

From doing a bit of hunting around, I think this can happen if you use escaped names (e.g. \a ) in textual views.
But hard to be sure without seeing your data. Maybe you can contact customer support?
Regards,
Andrew.
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Vote Up 0 Vote Down

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