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An Mixed-Sim(spectreverilog) Error: Component name (cdsNet0) not declared

Lynn Lou

Dear All,

I am trapped by a  spectreverilog error for sometime. I cannot do tran simulation, and in the output log, it says:

    Error! Component name (cdsNet0) not declared   [Verilog-CNNOD]

             "saveDefs", 6:  test.top.I0.cdsNet0

Could anyone help me out of this? Thank you in advance.

 

Parents

  • Hi Andrew,

    Thanks a lot for your reply.

    Would you please explain a bit more about "escaped names" ? Is it just a net name with a slash before it? You mean the symbol views when you mention about the "textual views"? It seems I did not use the escaped names in the Verilog codes, and the symbols are automatically generated.  

    Thank you very much.

     

    Best regards,

    Lynn 

Reply

  • Hi Andrew,

    Thanks a lot for your reply.

    Would you please explain a bit more about "escaped names" ? Is it just a net name with a slash before it? You mean the symbol views when you mention about the "textual views"? It seems I did not use the escaped names in the Verilog codes, and the symbols are automatically generated.  

    Thank you very much.

     

    Best regards,

    Lynn 

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