Stats

  • Locked Locked
  • Replies 2
  • Subscribers 65
  • Views 15209
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Vhdl-ams beginner

sebgimi

Hi,

 I'm really new in vhdl-ams, I write my firsts codes in this langage and I have some issues to understand some basics of this extension.

My tutor want me to describe an analogic comparator and test it with a ramp waveform. A schema of this circuit is in attachment.

I don't know how to connect the both entity like on the schema. What kind of type, class, mode I have to use for each port of each entity.

And above all how to simulate the hole component (ramp + comparator) in a testbench...

 Maybe my questions are surprising but I never study vhdl-ams in college so I have a large lack of informations that internet can't provide me...

Regards,

Sebastien

Parents

  • Hello Sebastien, 

    To create the ideal comparator in vhdl-ams is quite simple and straightforward.

    • The code should be something like this (depending if you want to have threshold or not).

    You can find the full code, test bench and simulation results on the source: ideal comparator  

    entity comparator is 
    GENERIC(
    Vthres : REAL := 0.1 --threshold
    ); 
    PORT(
    TERMINAL Vin : ELECTRICAL;
    TERMINAL Vref : ELECTRICAL;
    result : out std_logic
    );
    end entity comparator;

    ARCHITECTURE vhdlams of comparator IS 
    QUANTITY Volt ACROSS Vin TO Vref;
    BEGIN
    --result <= '1' when (Vin > Vref) else '0'; --without threshold
    result <= '1' when Volt'above(Vthres) else '0'; --With threshold 
    END vhdlams;

Reply

  • Hello Sebastien, 

    To create the ideal comparator in vhdl-ams is quite simple and straightforward.

    • The code should be something like this (depending if you want to have threshold or not).

    You can find the full code, test bench and simulation results on the source: ideal comparator  

    entity comparator is 
    GENERIC(
    Vthres : REAL := 0.1 --threshold
    ); 
    PORT(
    TERMINAL Vin : ELECTRICAL;
    TERMINAL Vref : ELECTRICAL;
    result : out std_logic
    );
    end entity comparator;

    ARCHITECTURE vhdlams of comparator IS 
    QUANTITY Volt ACROSS Vin TO Vref;
    BEGIN
    --result <= '1' when (Vin > Vref) else '0'; --without threshold
    result <= '1' when Volt'above(Vthres) else '0'; --With threshold 
    END vhdlams;

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.