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how to connect signal to a real_vector

sebgimi

Hi,

 I have some issues with a vhdl code. When I connect signals on an element of a real_vector I have these errors:

 ncvhdl -work st_lib -ams -message ../sources/systeme_comparateur_ent.vhdl ../sources/systeme_comparateur_arch.vhdl ../sources/systeme_comparateur_tb.vhdl
ncvhdl: 13.20-p002: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
../sources/systeme_comparateur_ent.vhdl:
        errors: 0, warnings: 0
../sources/systeme_comparateur_arch.vhdl:
                          S_mux1(0) => int1,
                                |
ncvhdl_p: *E,FMLBAD (../sources/systeme_comparateur_arch.vhdl,251|11): poorly formed formal part of element association 87[4.3.3.2] 93[4.3.2.2].
                          S_mux2(0) => int5,
                                |
ncvhdl_p: *E,FMLBAD (../sources/systeme_comparateur_arch.vhdl,274|11): poorly formed formal part of element association 87[4.3.3.2] 93[4.3.2.2].
                          S_mux3(0) => int13,
                                |
ncvhdl_p: *E,FMLBAD (../sources/systeme_comparateur_arch.vhdl,312|11): poorly formed formal part of element association 87[4.3.3.2] 93[4.3.2.2].
                          S_mux4(0) => int17,
                                |
ncvhdl_p: *E,FMLBAD (../sources/systeme_comparateur_arch.vhdl,335|11): poorly formed formal part of element association 87[4.3.3.2] 93[4.3.2.2].
        errors: 4, warnings: 0
../sources/systeme_comparateur_tb.vhdl:
        errors: 0, warnings: 0

My code is in attachment. In fact I want to connect real signals on each element of the real_vector in my code.

If you see something wrong, or if there is an other way to do this tell me please. 

  • You only provided part of the code (architecture, and no entity, plus none of the components being instantiated).

    It's hard to debug without seeing more - so probably going to customer support is your best bet. There's nothing particularly "AMS" about what you've shown, so I'm slightly tempted to move this to the functional verification forum, but I think customer support is better unless you can supply more of the example (if not all).

    Regards,

    Andrew.

  • My bad!

     I can provide you all the code you need.

    Sorry again for my post in the wrong forum

    vhdl.zip

  • OK, I'm not really a VHDL expert, but a little bit of experimentation and reading up gave me this. You need to do:

     signal S_mux1: real_vector (3 downto 0);

    and then:

        S_mux1 <= int1 & int2 & int3 & int4;
        mux1: analog_ADG704    
        
            generic map (INPUTS_SEL => 2)
        
            port map (En => enable_mux1,
                  A => A_mux1,
                  S => S_mux1,
    --              S_mux1(0) => int1,
    --              S_mux1(1) => int2,
    --              S_mux1(2) => int3,
    --              S_mux1(3) => int4,
                  D => mux1_mux5);

    Note that it doesn't make sense to do that S_mux1(0) stuff - because the interface to analog_ADG704 has ports En,A,S and D. So what is happening here is that I'm defining a signal with a continuous assign (I forget the terminology in VHDL) which concatenates the four reals into a 4 bit real_vector, and then that is port mapped to S.

    I didn't take care to ensure that the order is correct - I'll leave that to you to check and work out.

    Regards,

    Andrew.

  • Not a VHDL expert but you're totally right! Your solution is the good one!

    Thank you very much and sorry to have wasted your time.

     Regards,

     Sebastien

  • Sebastien,

    Not a waste of time, so no problem - it's always good to practice in something that's not my main area of expertise!

    Andrew.

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