Verilog In: Missing `define directives

I'm trying to import a verilog file containing multiple cell modules. Verilog In imports each cell module as a functional view in the appropriate cell, but the necessary `define directives from within a cell module are missing.

 For example, a cell module in this file looks like:

 `celldefine

`define EXAMPLE 1

module ...

...(`EXAMPLE is used)...

endmodule

`endcelldefine

The imported functional view contains the lines where `EXAMPLE appears, however, its `define statement is missing.

Is there an option for retaining the `define statements in the imported functional view?

Thanks