VPI within analog section

 Hi,

I'm trying to implement the VPIs in analog section.
My final goal is to implement a dynamic filling Table Lookup in a circuit simulator. Therfore I want to use the C-/C+ Structure as a Database and i need to call the vpi-function at everey call of the model.
Within an inital section, it is no problem to call the c-Funktion.
Within an analog section I get the error message below.
I'm not really sure if it is possible to call a VPI-routine within an analog section. The only example I found was in the VAMS-LRM: www.accellera.org/.../VAMS-LRM-2-4.pdf chapter: "12.22. Examples" page: 339(PDF), 324(Document). But I do not know where to find "vpiutils.h" and the example doesent work.

Do you know how to connect the VPI to a analog section?

Do you have other  examples?

 Do you haveother ideas?

Thank you very much


My AMS-Code is:

// resis.vams
`include "disciplines.vams"
module resist (p,n);
    parameter real r=30;
    inout p,n;
    electrical p,n;
    analog begin
        $hello;
        V(p,n) <+ r*I(p,n);
    end
endmodule

// vsrc.vams
`include "disciplines.vams"
module vsrc (p,n);
    parameter real dc=10;
    inout p,n;
    electrical p,n;
    analog
        V(p,n)<+dc;
endmodule

// top.vams
`include "disciplines.vams"
`include "resist.vams"
`include "vsrc.vams"
module top;    
    electrical p, gnd;
    ground gnd;
    resist #(.r(7)) R1(p,gnd);
    vsrc #(.dc(1)) V1(p,gnd);
endmodule


My C-File is:

//hello_vpi.c
#include <stdio.h>
#include "vpi_ams.h"
#include "vpi_user.h"
#include "vpi_user_cds.h"

void hello()
{
    printf("HELLO\n");
}

void register_hello()
{
    s_vpi_systf_data data;
    data.type = vpiSysTask;
    data.tfname ="$hello";
    data.calltf=hello;
    data.compiletf=0;
    data.sizetf=0;
    data.user_data=0;
    vpi_register_systf(&data);
}


My simulation control file is:

//scf.scs
myopt options rawfmt=psfbin
myinfo info what=oppoint where=rawfile
mytran tran stop=4u infoname=myinfo infotimes=[1u 2u 3u]


My commands are:

cd /home_ma/hos/Cadence/NC_Verilog/vpi_simple_circuit_01
gcc hello_vpi.c -fPIC -shared -o hello_vpi.so
ncverilog scf.scs top.vams +access+r -loadvpi ./hello_vpi.so:register_hello


My Error Message is:

irun(64): 13.10-s005: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
file: top.vams
    module worklib.resist:vams
        errors: 0, warnings: 0
    module worklib.vsrc:vams
        errors: 0, warnings: 0
    module worklib.top:vams
        errors: 0, warnings: 0
$CDSROOT = /eisoft/cadence/2013-2014/lnx86/INCISIVE_13.1
$TESTDIR = /home_ma/hos/Cadence/NC_Verilog/vpi_simple_circuit_01

TOOL:    ncsc(64)    13.10-s005
ncsc cc parameters:
    $CDSROOT/tools/cdsgcc/gcc/4.4/bin/gcc
    -I$CDSROOT/tools/include
    -I$CDSROOT/tools/inca/include-DNCSC
    -fPIC
    -c
    -x c  -Wall

ncsc: compiling $TESTDIR/hello_vpi.c

$TESTDIR/hello_vpi.c: In function 'register_hello':
$TESTDIR/hello_vpi.c:16: warning: assignment from incompatible pointer type

building library run.so

        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        top
    Discipline resolution Pass...
    Building instance overlay tables: .................... Done
    Building instance specific data structures.
    Loading native compiled code:     .................... Done
    Design hierarchy summary:
               Instances  Unique
        Modules:       3       3
        Interconnect:  2       -
    Writing initial simulation snapshot: worklib.top:vams
Loading snapshot worklib.top:vams .................... Done
    Starting analog simulation engine...
AMSD: Using spectre solver.

Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 12.1.1.080.isr11 64bit -- 25 Jul 2013
Copyright (C) 1989-2013 Cadence Design Systems, Inc. All rights reserved
        worldwide. Cadence, Virtuoso and Spectre are registered trademarks of
        Cadence Design Systems, Inc. All others are the property of their
        respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA
        Security, Inc.

User: hos   Host:   HostID:  PID:
Memory  available: 1.0687 GB  physical: 4.0176 GB
CPU Type: Intel(R) Core(TM)2 CPU          6700  @ 2.66GHz


Analog Kernel using -ANALOGCONTROL  scf.scs.
Reading file:
        /home_ma/hos/Cadence/NC_Verilog/vpi_simple_circuit_01/scf.scs
        $hello;
             |
ncsim: *E,SYFATAL (/home_ma/hos/Cadence/NC_Verilog/vpi_simple_circuit_01/resist.vams,8|7): `$hello' - Unsupported system task/function.

Error found by spectre during circuit read-in.
    ERROR (VACOMP-1816): Exiting AHDL compilation.
    ERROR (SPECTRE-356): AMS Analog Elaboration has exited with error.
        Simulation will terminate.

spectre terminated prematurely due to fatal error.
ncsim: *E,RNAERR: The simulator terminated with an analog initialization error.