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About the driving ability of digital circuits in spectreVerilog simulation.

xxgenerall over 11 years ago

Hi,

The circuit is like below. And notG is just a very simple verilog "not gate", which code is like this.

module (Vin,Vout);

input Vin;

output Vout;

assign Vout=~Vin;

endmodule;

xxgenerall over 11 years ago

With different loads, vout is also different. Like below,
- Tran.jpg
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xxgenerall over 11 years ago

How to set up the driving ability of digital circuits in spectreVerilog simulation?
Can anybody help me, please?
Thanks a lot.
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Tawna over 11 years ago

Hi,
You have posted this to the RF design forum.
This is a mixed-signal question which should be posted on the Mixed Signal forum.

Best regards,
Tawna
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Andrew Beckett over 11 years ago

I'll move the post to the right forum.
Andrew
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xxgenerall over 11 years ago

I'm so sorry, Ms. Tawna and Mr. Beckett.
It is the first mixed signal problem I'v encountered. And I did make a mistake. This will never happen again.
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