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Netlist should have explicit net definitions AMS

SimhanAnalog

We have a top module schematic which has a few blocks which are verilogams models. When we netlist the top module(using AMS OSS netlister) the netlist defines only interconnect buses and ports explicitly. We would like to see all interconnect wires defined explicitly. In addition to that we would like the netlist to have interconnects which connect two wreal ports as wreal instead of wire.

Here is an example to make our requirements clear.

We have a top level buffer_1x schematic with 2 ports(ind,outd). It contains two inverters cascaded. When we netlist the buffer_1x we get the following

module buffer_1x(ind,outd,vdd,vss);

input ind;

output outd;

inv_1x I_1( .ind(ind) , .outd(net1) );

inv_1x I_2( .ind(net1) , .outd(outd) );

endmodule

We want the netlister to define the intermediate net(net1) explicitly.

Moreover if the intermediate net connects two wreal ports we want it to be defined as wreal instead of wire.

The reason for requiring such a netlist is we use this netlist externally(say to run on FPGA) and since wreal is not recognized(synthesizable) we define wreal as a 24 bit(or more based on required accuracy). If all wreal are defined in netlist correctly then we just add a user-defined nettype wreal. But if the netlist provides some wreal as wire then we need to manually check and replace the wire with wreal and the process is error prone.


Kindly guide us to get such a netlist. We changed netlister to CBN but that also did not give us the required result. Or do we need to raise a request with cadence to add these two features?

  • This is not normally done because it's unnecessary, and it would potentially impede the normal discipline resolution process within the simulator.

    That said, the new UNL netlister does declare the wires in each module (CBN and OSS didn't). Again, not strictly necessary, but it's done for completeness and readability reasons.

    However, you can achieve what you want by adding a property on the wires you want to be declared as wreal. In the schematic, select the wire you want to be netlisted as wreal, bring up the Edit Properties form and add a user defined string property called netDiscipline with value wreal. This should work in all netlisters (I just checked it in UNL, OSS and CBN) - in each case it declares the net as wreal in that module.

    Regards,

    Andrew.

  • Thanks for your reply. By doing the change you suggested in schematic does it affect normal transistor level simulation where there are no ams models. What I mean is will the simulator add E2R and R2E because of this property?

    In my previous example I change the property of the wire connecting the two inverters to wreal. When I run transistor level simulation, will the simulator add E2R and R2E connect modules unnecessarily since it finds the wire to be wreal?

  • If you're running spectre as the simulator, then no, it wouldn't affect anything. However, if you're running with "ams" as the simulator, then it would have an impact because it would force that node to be wreal even if the blocks around it are transistor level.

    In that case you may need to add the property merely as a means of fixing the net. Alternatively you may need to modify the netlist by hand before using it outside of AMS?

    Regards,

    Andrew.

  • Thanks once again for the quick reply.

    I just ran a simple simulation in ams and the wreal net did not trigger connect modules when the blocks were transistor level. I guess the simulator was able to understand that the wreal net connects two electrical ports and did not require a connect module. Though we need to check this in a more complicated circuit.

    What did you mean by "In that case you may need to add the property merely as a means of fixing the net." ?

  • It was a typo. I meant to say "as a means of fixing the netlist". 

    As for the wreal netDiscipline - I suspect that because all the components on the net were electrical, it didn't force a connect module. Although I would be a bit cautious in case this behaviour changes in future...

    Regards,

    Andrew.

  • Hi Andrew,

            Thanks a lot for your quick replies.

    Narasimhan

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