Netlist should have explicit net definitions AMS

We have a top module schematic which has a few blocks which are verilogams models. When we netlist the top module(using AMS OSS netlister) the netlist defines only interconnect buses and ports explicitly. We would like to see all interconnect wires defined explicitly. In addition to that we would like the netlist to have interconnects which connect two wreal ports as wreal instead of wire.

Here is an example to make our requirements clear.

We have a top level buffer_1x schematic with 2 ports(ind,outd). It contains two inverters cascaded. When we netlist the buffer_1x we get the following

module buffer_1x(ind,outd,vdd,vss);

input ind;

output outd;

inv_1x I_1( .ind(ind) , .outd(net1) );

inv_1x I_2( .ind(net1) , .outd(outd) );

endmodule

We want the netlister to define the intermediate net(net1) explicitly.

Moreover if the intermediate net connects two wreal ports we want it to be defined as wreal instead of wire.

The reason for requiring such a netlist is we use this netlist externally(say to run on FPGA) and since wreal is not recognized(synthesizable) we define wreal as a 24 bit(or more based on required accuracy). If all wreal are defined in netlist correctly then we just add a user-defined nettype wreal. But if the netlist provides some wreal as wire then we need to manually check and replace the wire with wreal and the process is error prone.

Kindly guide us to get such a netlist. We changed netlister to CBN but that also did not give us the required result. Or do we need to raise a request with cadence to add these two features?