• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Mixed-Signal Design
  3. Resistance calculation of switch capacitor circuit

Stats

  • Locked Locked
  • Replies 4
  • Subscribers 63
  • Views 16720
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Resistance calculation of switch capacitor circuit

mkza1002
mkza1002 over 9 years ago

i am using cadence 6.1.5

I want to calculate resistance of a switch capacitor circuit using ladder topology.

i did dc analysis and plot Vs / Is  but difficult to calculate resistance from plot.

can anyone help me  with this

Thank you.

  • Cancel
  • Andrew Beckett
    Andrew Beckett over 9 years ago

    It rather depends what you mean by "resistance" - resistance from where to where? Some pictures would probably help.

    A DC analysis is not going to help, because a switch capacitor only has resistance by virtue of being switched. A DC operating point will only give you the currents and voltages for a static condition, and you'd need something like PSS (or one of the small signal analyses) to measure the time-averaged behaviour. I assume you understand the principles of switched capacitor design? 

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • mkza1002
    mkza1002 over 9 years ago

    Sir,

    This is my circuit  for realising large resistance(tera ohm) .

    this is n-stage circuit  I simulated for only 3 stage and i want to know the resistance between point A and B.

    can you  help me to know how to calculate ?

    and what analysis should be performed to get the results?

     thank you

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Andrew Beckett
    Andrew Beckett over 9 years ago

    I had been hoping to do some experiments, but lack of time to put together an example means that instead I'll just make a suggestion instead.

    What I think you probably should do is run a PSS analysis over your clock period (so the fundamental would be the frequency of the clock). Then set the PAC magnitude on the voltage source on the left.  You could set this to 1 - because it's a small signal analysis. Then save the current through this source and you can then plot 1/current from the PAC results to give the time-averaged impedance. I think that may be OK - probably worth checking with a single switch-capacitor stage and see if it's close to what you'd expect from theory.

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • mkza1002
    mkza1002 over 9 years ago
    Sir, thank you for your help.
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information