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SPICE file of layout showing ground and gate interchanged

Charanraj Mohan

Hi,

  I am beginner to Cadence. I am designing a simple CMOS inverter using UMC 130nm technology.

 I have a specific doubt in one of the flow of the design. After I do Calibre-LVS check and it passes successfully, I get a file in .sp format. Basically it is the SPICE netlist of the layout. I notice something strange in it. I found that in pMOS the drain and source got interchanged. But everything is rightly connected and the DRC, LVS and even PEX is also done. I really could't understand this, why the .sp file shows a wrong pin configuration for pMOS, but everything is fine.


 I can see that the layout is upside down, when I compare it with schematic in RVE, but it is correctly connected. Is there a top down approach for getting .sp file after LVC or something, that is still not clear. Or is it a bug, that needs to be fixed in Cadence for this particular design kit or something. Can someone give me an explanation for this ?

Thanks in advance.

  • I assume instead of "ground and source" you meant "drain and source"? If so, this is hardly surprising since generally MOS transistors (unless they are LDD (lightly doped drain) type devices) are symmetrical - so it's arbitrary which is the source and which is the drain. Looking at the geometries on the layout, they look the same - so the extraction rule deck (which is for a non-Cadence tool, by the way, so this is nothing to do with "Cadence", so wouldn't be a bug in our tools, assuming it's a bug at all) is most likely arbitrarily assigning one to be the source and one to be the drain.

    Regards,

    Andrew,.

  • Thanks Andrew. 'ground and source' was a typo error and i later corrected it. To b very specific, the below is the spice netlist of the Myinv.sp file after the Calibre-LVS is done. M0 out in grd grd N_12_HSL130E L=1.2e-07 W=2e-06 $X=2610 $Y=1715 $D=3
    M1 sup in out sup P_12_HSL130E L=1.2e-07 W=2e-06 $X=2610 $Y=3615 $D=4. The strange here is in pMOS-why the drain and source get exchanged. If the .sp file arbitrarily assigns the one as source and the other as drain of one/more pMOSFETS in the layout, can it confuse the designer at that particular stage, although the LVS passes and also everything works fine till end ? I think, may be this should be addressed to Calibre (Mentor Graphics).

  • I already explained this. The extraction rules have no means of knowing which of the two device pins is the source and which is the drain - they have the same geometries. So which way around it's connected is somewhat arbitrary, and generally the LVS rules would allow the source and drain to be permuted because of this reason which allows LVS to pass.

    It makes no difference to simulation.

    If the devices were non-symmetrical, then the extraction rules would be written to be able to identify which is specifically the source and which is specifically the drain - and if it was wrong in that situation, then it would be a problem with the rules (which are part of the PDK) rather than the extraction tool (most likely, at least, although it might be a tool bug).

    However, I suspect (as I said before) that this is just because the devices are symmetrical and so the source is indistinguishable from the drain, and is nothing to worry about.

    Regards,

    Andrew.

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