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SPICE file of layout showing ground and gate interchanged

Charanraj Mohan

Hi,

  I am beginner to Cadence. I am designing a simple CMOS inverter using UMC 130nm technology.

 I have a specific doubt in one of the flow of the design. After I do Calibre-LVS check and it passes successfully, I get a file in .sp format. Basically it is the SPICE netlist of the layout. I notice something strange in it. I found that in pMOS the drain and source got interchanged. But everything is rightly connected and the DRC, LVS and even PEX is also done. I really could't understand this, why the .sp file shows a wrong pin configuration for pMOS, but everything is fine.


 I can see that the layout is upside down, when I compare it with schematic in RVE, but it is correctly connected. Is there a top down approach for getting .sp file after LVC or something, that is still not clear. Or is it a bug, that needs to be fixed in Cadence for this particular design kit or something. Can someone give me an explanation for this ?

Thanks in advance.

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