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bulk-source or bulk-drain junction diode forward biased :-(

Charanraj Mohan

Hey,

 I am translating few schematics from 0.35um to 130nm. I found the difficulty in encountering warnings like 'the bulk-source or the bulk-drain junction diode is missing and it is forward biased'. How to encounter these critical warning where the simulations go abnormal. This happens only during a small time of the transient simulation. I don't need to use a bulk connection, rather how to tackle these kinda warnings ? I surfed a lot and couldn't find a right way or approach to tackle these in the schematic level. I am grateful to know if any such exists.

Thanks in advance.

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  • Charanraj Mohan

    Thanks Andrew.

    I went through it.
     And later found that it occurs mainly because of  high speed switching time of my test input signal in the schematic. For example, if i use 1ns of rise time or fall time, these warnings occur. When i use 100ns these warnings disappear. I would like to know if I can kick these warnings by some tuning setup in the ADE like when I use small abstol and small gmin, I get more accurate. I am saying this for an example.

    I want that the simulator should handle well the fast input pulse/switching too and give me no warnings. Is there any tuning parameters in the ADE ?

    Thanks in advance :-)

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  • Charanraj Mohan

    Thanks Andrew.

    I went through it.
     And later found that it occurs mainly because of  high speed switching time of my test input signal in the schematic. For example, if i use 1ns of rise time or fall time, these warnings occur. When i use 100ns these warnings disappear. I would like to know if I can kick these warnings by some tuning setup in the ADE like when I use small abstol and small gmin, I get more accurate. I am saying this for an example.

    I want that the simulator should handle well the fast input pulse/switching too and give me no warnings. Is there any tuning parameters in the ADE ?

    Thanks in advance :-)

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