Verilog-A to access wire bus of DUT

I am trying to create a verilog-A model to extract bus of nets of my DUT in a similar manner to the component deepprobe from analogLib in a Spectre transient simulation. These buses are at least 20-bit wide and it will be error-prone if I were to add them manually. I created a verilog-A block where I instantiate on the same level as my DUT and the code for the verilog-A is included below. If I try to use Cadence's verilogA editor,for the code below, I get the error "(TE-4309): extract failed for cellview "sandbox simCell_NetnameAccess veriloga". If I comment out the line "V(NetOfInterest01) <+ 1.0*V(NetNameInt);", extraction went smooth and transient simulation yield

  From testbench level, string name is IDUT.UCOMP_TOP.INT_CLK<0>

  From verilog-A level, string name is IDUT.UCOMP_TOP.INT_CLK<0>

is there something I need to do to process string to capture the triangular brackets?

thanks!

========== verilog-A code ==========

`include "constants.h"
`include "discipline.h"

module simCell_NetnameAccess(NetOfInterest01,NetOfInterest02);
  output NetOfInterest01,NetOfInterest02;
  electrical NetOfInterest01,NetOfInterest02;

  //parameter definition
  parameter string NetName = "DUT.XYZ";
  string NetNameInt = "IDUT.UCOMP_TOP.INT_CLK<0>";

  analog begin
    @(initial_step) begin
      $strobe("From testbench level, string name is %s\n", NetName);
      $strobe("From verilog-A level, string name is %s\n", NetNameInt);
    end // END of [ @(initial_step) ]

    V(NetOfInterest01) <+ 1.0*V(NetNameInt);
    V(NetOfInterest02) <+ 1.0*V(NetName);
  end // END of [ analog ]
endmodule