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How to make schematic CDF parameter become integer in AMS?

drdanmc

I have a block I often use in spectre simulations that takes a parameter and generates a bunch of voltages to provide configuration or trim bits.  The block has a CDF string parameter, "CODE", of type string with "parse as CEL" and "parse as number" both checked.  Then in my schematic for the block I have expressions like the following for bit 1:

((pPar("CODE")>>1) & 1)? 1 : 0

for the gain on analogLib/vcvs or dc value on an analogLib/vdc.  This works fine in spectre which interprets pPar("CODE") as an integer. 

I can also use

((int(pPar("CODE"))>>1) & 1)? 1 : 0

to be more explicit that it is an integer which is being shifted and bit-wise anded and spectre is still happy.

The problem lies when I use AMS as the simulator.  Now I get errors like:

file: ./netlist.vams
vcvs #(.gain(((CODE>>1)&1)?1:0)) E1 (SRC[1], VSS, VDD, VSS);
|
ncvlog: *E,NOSHRL (./netlist.vams,29|22): Illegal type real shift operand (left operand) [4.1.1][4.1.12(IEEE)].
vcvs #(.gain(((CODE>>1)&1)?1:0)) E1 (SRC[1], VSS, VDD, VSS);
|
ncvlog: *E,BDRLLO (./netlist.vams,29|34): Illegal type real left operand to & (bit-wise AND) operator [4.1(IEEE)].

and if I try adding in that int() in the schematic, the netlister converts to real2int() and I get:

file: ./netlist.vams
vcvs #(.gain(((real2int(CODE)>>1)&1)?1:0)) E1 (SRC[1], VSS, VDD, VSS);
|
ncvlog: *E,NOSHRL (./netlist.vams,29|22): Illegal type real shift operand (left operand) [4.1.1][4.1.12(IEEE)].
vcvs #(.gain(((real2int(trimCode)>>1)&1)?1:0)) E1 (SRC[1], VSS, VDD, VSS);
|
ncvlog: *E,BDRLLO (./netlist.vams,29|34): Illegal type real left operand to & (bit-wise AND) operator [4.1(IEEE)].

I can't change the parameter type to integer in the CDF because this precludes me from using a design variable to specify the CODE value. 

So.... is there an expression I can use in a schematic that will work correctly for both spectre and AMS?  I it comes down to it I can create an AMS view for the cell but I'd hoped to not add additional views if not needed.

Parents

  • Hi Dan,

    This only happens for me if you eventually set the parameter to be a design variable. In other words, the netlister does not set the type of the parameter passed into the Verilog-AMS module, and I only get the error if the passed parameter ultimately gets passed a real number. So say that the instance of the block as you've described has the CDF parameter CODE set to MYCODE then the AMS netlister netlists MYCODE in the cds_globals module as:

    // Design Variables
      dynamicparam real MYCODE = 43;

    It's this that then causes the problem. Luckily there's an option on Simulation->Options->AMS Simulator which allows you to define variables to be netlisted as integer:

    This resolves the problem altogether.

    I have a component bussetp (described in this article: Creating a component that allows setting a value on a bus in an analog simulation) which works in a similar fashion. I probably should update that article to mention the need for top level design variables to be netlisted as integer...

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Yes, indeed, I was ultimately using a design variable.  Thanks for the tip.  I'd missed that option in the netlister.  It works now.

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