• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Mixed-Signal Design
  3. define different but related parameters in array of stimuli...

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 64
  • Views 13925
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

define different but related parameters in array of stimuli to ADE

CSCNalu
CSCNalu over 6 years ago

Hi

I'm trying to simulate a rather large part of my design that expects 128 inputs that are all delayed from each other (sequenced in order) that basically turn on switches.  Is there an easy way to define this in the schematic cell with an analogLib part?  Basically I need a pulse of a fixed length but I want the delay to be cascaded.

I know how to make an array of 128 vsource stimuli but I'd rather not make 128 different sources that go to 128 different nets that have 128 (1:1:127) * delay as the start up.

Thanks

Chris

  • Cancel
  • Andrew Beckett
    Andrew Beckett over 6 years ago

    Hi Chris,

    I'd do this with a Verilog-A model:

    // VerilogA for mylib, delayedSrcs, veriloga
    
    `include "constants.vams"
    `include "disciplines.vams"
    `define NUMBITS 128
    module delayedSrcs(src);
    output [`NUMBITS-1:0] src;
    electrical [`NUMBITS-1:0] src;
    
    parameter real td=10n;      // initial delay
    parameter real trf=1n;      // rise and fall time
    parameter real offset=50n;  // offset delay between bits
    parameter real val0=0.0;    // low voltage
    parameter real val1=1.2;    // high voltage
    parameter real width=100n;  // width of pulse. Set to 0 if you don't want it to go low again
    parameter real period=0.0;  // period of pulse once started. 0 means one shot (not periodic)
    
    integer srcVal;
    genvar bit;
    
    analog begin
        // if period is 0, then the pulse is a one-shot. Otherwise it's
        // periodic
        @(timer(td,period)) begin
            srcVal=1;
        end
        // this allows the pulse to return to 0. If you don't want that
        // set the width parameter to (can be set on the instance)
        @(timer(td+trf+width,period)) begin
            if (width>0) begin
                srcVal=0;
            end
        end
        // Generate all the delayed sources
        for(bit=0; bit<`NUMBITS; bit=bit+1) begin
            V(src[bit]) <+ transition(srcVal*(val1-val0)+val0,offset*bit,trf);
        end
    
    end
    
    endmodule

    If you create a Verilog-A view inside Virtuoso (I called the cell "delayedSrcs"), it will then ask you to create a symbol. When you instantiate it, you can use the "Tool Filter" to see the parameters - you might in your case want to set width to 0 on the instance if you don't want the pulses to return to 0 after going high.

    Another possibility would have been to create a schematic PCell, but I think the VerilogA approach is simpler in this case.

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • CSCNalu
    CSCNalu over 6 years ago in reply to Andrew Beckett

    Hi Andrew

    Thanks - that's incredibly helpful.  Didn't even know I could do anything like this; this should be fun.

    Chris

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information