I'm trying to simulate a rather large part of my design that expects 128 inputs that are all delayed from each other (sequenced in order) that basically turn on switches. Is there an easy way to define this in the schematic cell with an analogLib part? Basically I need a pulse of a fixed length but I want the delay to be cascaded.
I know how to make an array of 128 vsource stimuli but I'd rather not make 128 different sources that go to 128 different nets that have 128 (1:1:127) * delay as the start up.
I'd do this with a Verilog-A model:
// VerilogA for mylib, delayedSrcs, veriloga
`define NUMBITS 128
output [`NUMBITS-1:0] src;
electrical [`NUMBITS-1:0] src;
parameter real td=10n; // initial delay
parameter real trf=1n; // rise and fall time
parameter real offset=50n; // offset delay between bits
parameter real val0=0.0; // low voltage
parameter real val1=1.2; // high voltage
parameter real width=100n; // width of pulse. Set to 0 if you don't want it to go low again
parameter real period=0.0; // period of pulse once started. 0 means one shot (not periodic)
// if period is 0, then the pulse is a one-shot. Otherwise it's
// this allows the pulse to return to 0. If you don't want that
// set the width parameter to (can be set on the instance)
if (width>0) begin
// Generate all the delayed sources
for(bit=0; bit<`NUMBITS; bit=bit+1) begin
V(src[bit]) <+ transition(srcVal*(val1-val0)+val0,offset*bit,trf);
If you create a Verilog-A view inside Virtuoso (I called the cell "delayedSrcs"), it will then ask you to create a symbol. When you instantiate it, you can use the "Tool Filter" to see the parameters - you might in your case want to set width to 0 on the instance if you don't want the pulses to return to 0 after going high.
Another possibility would have been to create a schematic PCell, but I think the VerilogA approach is simpler in this case.
Thanks - that's incredibly helpful. Didn't even know I could do anything like this; this should be fun.