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  3. Format of "VCD Info File"

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Format of "VCD Info File"

pyohayo
pyohayo over 6 years ago

Hello,

Does exist a document with examples on how to create  "VCD Info File" for a given "VCD File"?

Thanks

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  • pyohayo
    pyohayo over 6 years ago

    Well ... I've found a description in Appendix E of Spectre® Circuit Simulator and Accelerated Parallel Simulator User Guide

    and created vcd_info file according to the this document.

    Here is the content of the vcd_info :

    .voh 5.0

    .vol 0.0

    .scope simple_clock(bhv)

    .out clock

    where simple_clock(bhv) - the name of digital block entity(architecture) from which I creaed vcd.

    clock - the only output from the block.

    At the Virtupso side the schematic is very simple: only one component - resistor, connected to GND at one side, at other - to the floating net named "clock".

    When I run Spectre, I get the following:

    Notice from spectre during topology check.
    Only one connection to the following 2 nodes:
    0
    clock
    Error found by spectre during initial setup.
    ERROR (USIMPRS-17866): No Data read from the vcd file, please verify that the scopes are correct and there are in and/or out vectors specified.
    Fatal error found by spectre during initial setup.
    FATAL (SPECTRE-13004):

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  • pyohayo
    pyohayo over 6 years ago in reply to pyohayo

    When trying the setup from previous message, I erroneously worked with wrong file.

    Here is setup that simulates, but still there is no connection between stimuli signal and node in Virtuoso schematic.

    The top of .vcd file:

    $comment
    TOOL: simvision(64) 12.10-s019
    $end

    $date
    Jul 01, 2019 15:18:55
    $end

    $timescale
    1fs
    $end


    $scope module simple_clock $end
    $var wire 1 ! clock1 $end
    $upscope $end

    $enddefinitions $end
    #0
    $dumpvars
    0!
    $end
    #50000000
    1!
    #100000000
    0!
    #150000000
    1!
    #200000000

    ..........

    The content of vcd_info:

    .hier 1
    .voh 5.0
    .vol 0.0

    .scope simple_clock
    .out clock1

    Note from simulation log:

    Only one connection to the following 2 nodes:

    0

    clock1

    As result - the clock1 is kept to 0.

    Any comments.

    Thanks

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  • Andrew Beckett
    Andrew Beckett over 6 years ago in reply to pyohayo

    The issue is that you should have used .in rather than .out. From the same document you referenced (right at the beginning):

    The signal directions are specified in the signal information file. To input signals, Spectre applies stimuli to the simulation. The values of the output signals are used to perform a vector check against the simulation results, and vector errors are generated if mismatches occur

    I've not really tried the checking capability with Spectre (I know I've used it with UltraSim in the past), but the key point here is that if you're expecting the signal to be driven, you must specify .in so that it's an input signal.

    Andrew.

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  • pyohayo
    pyohayo over 6 years ago in reply to Andrew Beckett

    Thanks Andrew,

    The case that interests me isn't mentionned in the fragment you quote. i.e. when digital stimuli in .vcd file are applied to Spectre simulator.

    Or such case isn't taken into consideration by Cadence.

    Anyway I've tried with .in.

    The same result

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  • pyohayo
    pyohayo over 6 years ago in reply to pyohayo

    Well, actually I don't understand what really happens ... I modify the content of the vcd_info and .vcd (e.g. change the name of signal) and rerun simulation, but simulator always shows the same message as if it dodn't see modifications.

    So after each modification should I close and reopen ADE ?

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  • Andrew Beckett
    Andrew Beckett over 6 years ago in reply to pyohayo

    Hit the stop button in ADE. Normally ADE (L) keeps spectre running and most likely it's not refreshing if the contents change.

    It does work with .in. If I use this:

    .hier 1
    .vih 5.0
    .vil 0.0

    .scope simple_clock
    .in clock1

    Then I get a signal called simple_clock.clock1 - i.e. a signal inside the hierarchical instance called simple_clock (which gets created if it doesn't exist in your design).You should also use vih/vil rather than voh/vol. It's not going to drive a top level signal called clock1. If you wanted that, you need to use .hier 0 instead. Or add:

    .alias simple_clock.clock1 clock1

    The checking of output vectors does indeed work with spectre (I just checked) - I get a file called input_tran.vecerr with the details of any mismatch between the signals marked as outputs and the actual signals in the simulation - so it's to check that the response is what you expect.

    For more details, look at the Rapid Adoption Kit Using VEC and VCD files in AMS and Analog Simulation in ADE

    Regards,

    Andrew.

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  • pyohayo
    pyohayo over 6 years ago in reply to Andrew Beckett

    Yes !!!

    Thanks Andrew !

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  • pyohayo
    pyohayo over 6 years ago in reply to Andrew Beckett

    Yes !!!

    Thanks Andrew !

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