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  3. vector net cannot be connected to a spice/spectre instance...

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vector net cannot be connected to a spice/spectre instance by port name

PrasadAMSEng
PrasadAMSEng over 5 years ago

Cell CELL1 is instantiated in design TOP1 to run ams simulation on design TOP1 with dspf netlist of CELL1. dspf netlist of CELL1 is provided in config view through "Specify Spice source file". The given dspf file is properly read by tool. 

     Problem comes with the verilogAMS netlist when CELL1 has bus ports, for example sig<2:0>.  The instantiation of CELL1 in netlist.vams is  I10 CELL1( .sig(net1[2:0]) )

xrun throws error that vector net cannot be connected to a spice/spectre instance by port name

Thanks & Regards,

Prasad

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  • Andrew Beckett
    Andrew Beckett over 5 years ago

    Suggest you use View->Properties and enter the sourcefile_opts field for the DSPF-included cell. You might also want to search in the documentation (e.g. in the box at the top of the Help menu in Virtuoso) for “sourcefile_opts” to see the syntax.

    Alternatively in the ADE window, use Setup->Simulation Files and use the DSPF part there (this also allows control over bus delimiters).

    This appears to be related to your other post? Not sure if both need answering?

    Andrew

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  • J S Mason
    J S Mason over 5 years ago in reply to Andrew Beckett

    I see a similar problem using ams ( with irun ) where I am pointing to a digital block which I have converted to spice using v2lvs with the -e option. When I run the sim then I see 'Vector net cannot be connected to a Spice/Spectre instance by port name.' How do you suggest the problem gets fixed in this case?

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  • Andrew Beckett
    Andrew Beckett over 5 years ago in reply to J S Mason

    I can't comment on any options for v2lvs because this is a Mentor tool and so I don't know how it works or what the -e option is for. However, why are you converting the Verilog to SPICE? Why not just include the Verilog in the AMS simulation?

    If you really do need to use the SPICE representation, how are you including the SPICE into the AMS simulation? Are you using the hierarchy editor? If so, are you specifying any sourcefile_opts that I mentioned before?

    This really would be best handled via customer support as then we can see the actual data you're using which would remove a lot of guesswork.

    Thanks,

    Andrew.

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  • Andrew Beckett
    Andrew Beckett over 5 years ago in reply to J S Mason

    I can't comment on any options for v2lvs because this is a Mentor tool and so I don't know how it works or what the -e option is for. However, why are you converting the Verilog to SPICE? Why not just include the Verilog in the AMS simulation?

    If you really do need to use the SPICE representation, how are you including the SPICE into the AMS simulation? Are you using the hierarchy editor? If so, are you specifying any sourcefile_opts that I mentioned before?

    This really would be best handled via customer support as then we can see the actual data you're using which would remove a lot of guesswork.

    Thanks,

    Andrew.

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  • J S Mason
    J S Mason over 5 years ago in reply to Andrew Beckett

     I included the Spice netlist for the digital top level using specify spice source file in the config view and the included logic cells would be referenced by including their spice library as a defnition file within the ams simulation files setup. I want a Spice representation since I am interested in a static dc current problem. I could raise a case via customer support but was trying to see if a similar issue had previously been reported and came across this forum note.

    Thanks, James

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