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  3. Is there an eval command in Verilog-a?

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Is there an eval command in Verilog-a?

LDIL
LDIL over 5 years ago

Hello all.

Is there a command in Verilog-a, which accepts a string, and evaluates it as code, like in SKILL/TCL?

I don't think so, but wanted to make sure.

Thanks.

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  • Andrew Beckett
    Andrew Beckett over 5 years ago

    No. I'm not sure how this would be useful - Verilog-A is not a general purpose programming language, so doing things like this at run time would be a bit odd...

    Andrew

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  • Andrew Beckett
    Andrew Beckett over 5 years ago

    No. I'm not sure how this would be useful - Verilog-A is not a general purpose programming language, so doing things like this at run time would be a bit odd...

    Andrew

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  • LDIL
    LDIL over 5 years ago in reply to Andrew Beckett

    True. But odd does equate useless... It is intended for debug pruposes, not for normal run, where performance is paramount. Compiled languages are harder to get something like this done, and hardware languages in particular, usually won't need that. The LRM showed nothing of the kind, but it is better to ask than to double check.

    Thanks, and enjoy the weekend before I interrupted it.

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  • Andrew Beckett
    Andrew Beckett over 5 years ago in reply to LDIL

    This isn't really because Verilog-A is compiled (because that's an implementation choice for performance), but more that it's a hardware description language. Changing the description of the hardware (as this would then be doing) would be hard anyway, especially as this might involve a change in the matrix formulation that needs to be solved.

    Anyway, no problem for interrupting my weekend!

    Regards,

    Andrew.

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