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Best practices for Verilog-a modelling time variant resistance

Hello all.

I am simulating a design with time variant resistor, which values can be in [oHM] from thousands to even millions. I now set it as a simple real.

What is the best practice for assigning values/ setups for it, in order to have no convergence issues or runtime issues?

I mean, usually the voltage is no more than 5V, and the currents are less than 1e-2.

Thanks.

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Frank Wiedmann over 5 years ago

General advice for behavioral modeling can be found in chapter 3 "AMS Behavioral Modeling" of the "Mixed-Signal Methodology Guide". This chapter was written by Ron Vogelsong from Cadence and can be downloaded (in four parts) from https://www.eetimes.com/book-excerpt-mixed-signal-methodology-guide-part-4/#. Especially the section "Modeling Best Practices Considerations" contains lots of valuable advice. Another excellent resource is the article "Best Practices for Compact Modeling in Verilog-A" by Colin McAndrew et al. which is in Open Access and can be downloaded from https://ieeexplore.ieee.org/document/7154394.
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Frank Wiedmann over 5 years ago

General advice for behavioral modeling can be found in chapter 3 "AMS Behavioral Modeling" of the "Mixed-Signal Methodology Guide". This chapter was written by Ron Vogelsong from Cadence and can be downloaded (in four parts) from https://www.eetimes.com/book-excerpt-mixed-signal-methodology-guide-part-4/#. Especially the section "Modeling Best Practices Considerations" contains lots of valuable advice. Another excellent resource is the article "Best Practices for Compact Modeling in Verilog-A" by Colin McAndrew et al. which is in Open Access and can be downloaded from https://ieeexplore.ieee.org/document/7154394.
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