Need help on identifying issue with VerilogAMS issue

Setup a testbench with config view and a verilogams block which will drive test signals towards my analog stuff.

right now I am making a very simple cell in verilogams, its basically a unit which drives 10ns clock.

inside the testbench i defined a module which takes that clock and converts it to continuous signal for my analog circuit.

Below is a code:

//Verilog-AMS HDL for "libtest", "ams_test1" "verilogams"

`include "constants.vams"
`include "disciplines.vams"

module signal_d2a (in, out);
reg in;
electrical out;

parameter real trise=2n, tfall=2n;
parameter real digOutHigh = 5.0, digOutLow = 0.0;
integer logicState;

analog begin

if (in == 1'b1)
logicState = digOutHigh;
else
logicState = digOutLow;

V(out) <+ transition(logicState, 0, trise, tfall);
end
endmodule

module ams_test1 (
out );

output out;

wire outsig;
reg clko;

signal_d2a out1(
.in(clko),
.out(outsig) );

initial

begin
clko=0;
end

always
#5 clko = !clko;

assign out = outsig;

endmodule

I am getting following error, and not understanding what exactly is wrong:

xmelab: *E,CUVMUR (/proj/ams_test1/verilogams/verilog.vams,36|14): instance 'ams_testbench1.I0@ams_test1<module>.out1' of design unit 'signal_d2a' is unresolved in 'libtest.ams_test1:verilogams'.

Any idea what exactly i am doing wrong? again, its basically a "clock" generator, and a function to transition it from purely discrete to continuous signal.