Getting a High Frequency toggling at PFD output

Dear Kulmani,

Kulmani said:

To model the dead zone of PFD i am adding some delay of 15ps to the AND gate logic as in the code.

When i am simulating the above circuit, when CLK_FB and CLK_REF both are high i am getting a very high frequency toggling till one of them goes low as shown in the above plot. I am unable to understand the issue here. 

When i am not giving the delay in AND gate i see spike like toggling instead. Somewhat like this : 

Maybe I am overlooking something, but as I reviewed your veriloga code for both the DFF and AND gate, I find the propagation delay times of each are assigned as 0.0. I don't see the 15 ps delay times you mentioned in your post.

From the two relevant sections of code:

DFF:

-----------------

real tdelay_clkq=0,tfall=1p,trise=1p; // rise and fall time of the output kept as 1p, clk to q delay is kept 15p as per the dead zone

...

V(Q) <+ transition(q_int ? 0.9 : 0, tdelay_clkq, trise,tfall);

AND gate:

--------------------------

real tdelay_and=0,tfall=1p,trise=1p;

....

V(out) <+ transition(d_out ? 0.9 : 0, tdelay_and, trise,tfall);

--------------------------

With zero propagation delay times for each, I believe you will observe an oscillation at the time step of the simulator as the output of the AND gate will occur at the exact same time as its input changes - since the time delay afforded the combination of the AND gate propagation delay time and DFF propagation delay times is 0.0. 

Am I misinterpreting your comments concerning the use of a 15 ps delay time in the AND gate and  clock to Q delay time of the DFF? My apologies if I am!

Shawn

Hi Shawn,

Thank you for the reply.I agree to your point, actually in the above code delay is kept 0 and i am getting a spike like oscillation as i have attached the snapshot for. That is happening when no delay is there. But when i give a 15ps of delay then the oscillation would still be there and instead have a pulse width of 15ps as per the delay of the AND+DFF, i want to avoid this particular toggling. I want to achieve functionality of a PFD and in doing so this is coming out to be a blockage for me.

Attaching a zoomed in snap for your reference when i am giving a 15p delay : 

Regards,

Kulmani

Dear Kulmani,

But when i give a 15ps of delay then the oscillation would still be there and instead have a pulse width of 15ps as per the delay of the AND+DFF

Kulmani said:

.I agree to your point, actually in the above code delay is kept 0 and i am getting a spike like oscillation as i have attached the snapshot for.

Thank you for clarifying your post Kulmani!

Kulmani said:

But when i give a 15ps of delay then the oscillation would still be there and instead have a pulse width of 15ps as per the delay of the AND+DFF

Yes. I reviewed your code again, and it appears the issue may be with your implementation of the reset function. You define an internal signal d_en_rst

as shown below:

@(cross( V(RST) - V(AVDD)/2 , 1 )) d_en_rst=1; // Identifying RST level
@(cross( V(RST) - V(AVDD)/2 , -1)) d_en_rst=0; // Identifying RST level

However, your comment suggest the RST input is intended to be level sensitive but your definition is one where the signal d_en_rst will be set to 1 when your input RST crosses the threshold AVDD/2 with a rising edge (positive slope) and will be set to 0 only when the input RST crosses the threshold AVDD/2 with a falling edge (negative slope). However, I believe in the PFD implemtation the RST input needs to be a level sensitive - NOT an edge sensitive input. In your case, and with reference to your circuit diagram and figure in your latest post, I';ve annotated a version of the fiugre to detail the problem and included it as Figure 1.

As an alternative to your implementation in your posted veriloga code, I might suggest you study the level sensitive reset DFF code provided by Ken Kundert at URL:

https://designers-guide.org/verilog-ams/rf-models/dff/dff.va

or simply include a pointer to his verilog in lieu of your implemention in your PFD (assuming you don't need the enable function to verify proper PFD operation.

Otherwise, I think you need to correct your veriloga to make the RST input an asynchronous and level sensitive input and not an edge sensitive input. Let me know your thoughts Kulmani...I hope this provides some insight.

Shawn

Figure 1

Hi Shawn,

Thank you for your detailed response. I really appreciate this.

Yes as you pointed out correctly, it is a level triggering issue.

What i figured out is when my CLK goes high as it is edge triggered, the flag corresponding to that clock goes high and for the entire duration of Pulse Width High remains high, and when reset comes it tries to pull down my outputs but at the same time CLK flag being high pulls it up again in next time step so hence we were getting this oscillation kind of a situation. 

For the solution part what i have done is i am making my CLK flag low once the data has been assigned high value which in turn stops my output to rising again when RST goes high and keeps it in LOW state which is expected for RST condition.

Here is  the modification that is working for me as of now : 

if (d_en_clk) begin
q_int=d_high;

d_en_clk=0;
end

With the above change my PFD outputs seems to be working fine.

Thank you Shawn for your valuable inputs, it did give me a perspective to the problem and helped me debug it further. 

Also i would like to mention here that the dedication with which you help everyone on this forum truly shows your love for what you do. Its really commendable. Keep it going ! Many Thanks from all of us ! 

Dear Kulmani,

Kulmani said:

With the above change my PFD outputs seems to be working fine.

Excellent! Thank you, so much, for letting us know your issue is resolved!

I only wish I was deserving of your very kind comments...it is people like Andrew and Frank and the other experts who are far more deserving than I!

Shawn