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  3. RLC series circuit

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RLC series circuit

vshnkmr
vshnkmr over 3 years ago

Hi,

Can somebody tell me how to plot  both the magnitude and phase behavior of the loop current and the voltage across resistor, capacitor and inductor over a  frequency range of 1mHz to 1MHz .

I have made the schematic , but dont know how to plot. can somebody help me with it giving detailed step. I am new to this , please help me.

Kind Regards

R.Vishnu Kumar

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  • Andrew Beckett
    Andrew Beckett over 3 years ago

    Which tool and software version are you using?

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  • Andrew Beckett
    Andrew Beckett over 3 years ago

    Which tool and software version are you using?

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  • vshnkmr
    vshnkmr over 3 years ago in reply to Andrew Beckett

    Hi, 

    I am using cadence virtuoso. 

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  • vshnkmr
    vshnkmr over 3 years ago in reply to vshnkmr

    Virtuoso 6.1.8

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  • vshnkmr
    vshnkmr over 3 years ago in reply to Andrew Beckett

    Virtuoso 6.1.8

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  • ShawnLogan
    ShawnLogan over 3 years ago in reply to vshnkmr

    Dear vshnkmr,

    vshnkmr said:
    Virtuoso 6.1.8

    Since that version of Virtuoso supports ADE Assembler and Explorer, I will assume you are using one of those ADE simulator tools. Hence, I have assembled a set of instructions in the Portable Document Formatted file at URL:

    https://ent.box.com/s/4tf0zyzv09vxfkcdv4ajdquw0ss9j1i7

    (Link will expire at the end of 2021)

     I also have attached a compressed (".zip") file. If you unzip this file, the comma-separated variable files of both test bench variables and test bench outputs are included that you may import into your maestro Explorer view IF the net names are the same as your Virtuoso test bench. If note, you may first edit each file to change the net names to those in your Virtuoso schematic and then import them. I included instructions as to how to import the outputs file in the Portable Document Formatted file. I hope the instructions are sufficiently clear to provide you with the insight you need.

    Shawn

    outputs_variables_in_rlc_test_bench_sml_110621.zip

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