Allowed amount of input wreal data type

I wanted to use the source code option in this forum but it didn't work:)))) sorry

I write it again below

////////////////////////////////////////////////////////////////////////

`include "constants.vams"
`include "disciplines.vams"

module wreal_test (in,out,clk );
    input in,clk;
    output reg [0:7]  out;
    wreal in;
    integer i ;
    real sample;
//    assign out=0;
        always @(posedge clk)
        begin
            sample = in;
            if (0<sample<1)
                out=8'b00000001;
                
            else if (1<sample<2)
                out = 8'b00000010;
            else if (2<sample<3)
                out = 8'b00000011;
            else if (3<in<4)
                out = 8'b00000100;
            else if (4<in<5)
                out = 8'b00000101;
            else
                out = 8'b00000000;

        end
                    



endmodule

dozen people saw this question but no one hadn't paid attention that we cant write "if(0<in<1)" .
yeah I know that's a shitty mistake for programmers but I didn't get any error so I thought that it was not a problem.

Dear marzi,

marzi said:

dozen people saw this question but no one hadn't paid attention that we cant write "if(0<in<1)" .
yeah I know that's a shitty mistake for programmers but I didn't get any error so I thought that it was not a problem.

I did see your initial post, but your question was not clear to me and hence I did not respond. I have since read your two additional posts and still do not fully understand what you are asking and do not understand your comment:

"... that we cant write "if(0<in<1).

yeah I know that's a shitty mistake for programmers but I didn't get any error so I thought that it was not a problem."

Nevertheless, I am assuming perhaps you are experiencing some type of error when using your code for an 8 bit ADC.  You only indicate the code "didn't work" so I do not understand what type of error you are observing. Is it a compiling error? Is the conversion not what you expect? What are the inputs and outputs connected to?

Since I don't know these answers, all I can do is provide a sample code for an 8 bit ADC that I have used for years in both DC and transient analyses with the hope you can modify it for your use. The code is shown below.

Shawn

// VerilogA for simple transient compatible eightbit_ad,
// sml 8/10/2020


`include "constants.vams"
`include "disciplines.vams"

module eightbit_ad(VOUT, VDD, VIN, VSS);
output [7:0] VOUT;
electrical [7:0] VOUT;
input VDD;
electrical VDD;
input VIN;
electrical VIN;
input VSS;
electrical VSS;
integer vin_integer;
parameter real rise_fall_time = 50e-12;
integer vout[7:0];

   analog begin
   
   vin_integer = V(VIN,VSS);

   if (vin_integer%256<128) V(VOUT[7],VSS)<+V(VSS);
      else V(VOUT[7],VSS)<+V(VDD,VSS);   
   V(VOUT[7],VSS)<+ transition(V(VDD)*vout[7],rise_fall_time,rise_fall_time);

   if (vin_integer%128<64) V(VOUT[6],VSS)<+V(VSS);
      else V(VOUT[6],VSS)<+V(VDD,VSS);   
   V(VOUT[6],VSS)<+ transition(V(VDD)*vout[6],rise_fall_time,rise_fall_time);

   if (vin_integer%64<32) V(VOUT[5],VSS)<+V(VSS);
      else V(VOUT[5],VSS)<+V(VDD,VSS);   
   V(VOUT[5],VSS)<+ transition(V(VDD)*vout[5],rise_fall_time,rise_fall_time);

   if (vin_integer%32<16) V(VOUT[4],VSS)<+V(VSS);
      else V(VOUT[4],VSS)<+V(VDD,VSS);   
   V(VOUT[4],VSS)<+ transition(V(VDD)*vout[4],rise_fall_time,rise_fall_time);
   
   if (vin_integer%16<8) V(VOUT[3],VSS)<+V(VSS);
      else V(VOUT[3],VSS)<+V(VDD,VSS);   
   V(VOUT[3],VSS)<+ transition(V(VDD)*vout[3],rise_fall_time,rise_fall_time);

   if (vin_integer%8<4) V(VOUT[2],VSS)<+V(VSS);
      else V(VOUT[2],VSS)<+V(VDD,VSS);   
   V(VOUT[2],VSS)<+ transition(V(VDD)*vout[2],rise_fall_time,rise_fall_time);

   if (vin_integer%4<2) vout[1]=0;
      else vout[1]=1;
   V(VOUT[1],VSS)<+ transition(V(VDD)*vout[1],rise_fall_time,rise_fall_time);

   if (vin_integer%2<1) vout[0]=0;
      else vout[0]=1;
   V(VOUT[0],VSS)<+ transition(V(VDD)*vout[0],rise_fall_time,rise_fall_time);
   
   end
   
endmodule

hi Shawn
 I really appreciate your reply. I was thinking that I'm talking to myself because no one said anything:)
as you said "

Unknown said:

What are the inputs and outputs connected to?

"I had written about my inputs  " 

marzi said:

I arranged a test bench for my code that the inputs are a sine voltage with 6 V amplitude and a clock signal for Sequential circuit in verilog code.

"Also I said I'm getting a result that is not my expectation and I didn't say anything about the error because I didn't have any errors :)
In my second reply which I explain my mistake, every programmer knows that this conditional for if (0<in<2) is not correct because it should be like this (in>0 & in<2), and it's an obvious mistake. I was struggling with the concept of wreal type(because I'm a newbie at verilog-ams) and I didn't pay attention to this obvious mistake.
In the end, as I said I really appreciate your reply and your time.
sincerely
marzi

marzi said:

I really appreciate your reply. I was thinking that I'm talking to myself because no one said anything:)

Hi Marzi,

One thing to realise is that this forum is responded to by the community - including those of us that happen to work for Cadence. It's not part of my role at Cadence to answer here - but I do what I can to help. I was just extraordinarily busy this week and hence didn't even have a chance to look at your question, let alone answer it. I'm sure that's the same for many others.

If you need urgent help, you should contact customer support. We do what we can to help in these forums though!

Thanks,

Andrew

hi Andrew
I've seen every time that you answered lots of questions on this forum, I know you are kind to everyone.
yeah, I've got that you are busy, I was just joking :)
thanks for your effort for all of us on this forum.
 lots of times you've been my hero about errors on my way;)