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SystemVerilog: Assign a array to a bus

HoWei

Hi,

I want to assign an array of sigals to an output bus, as in the example below.

The order of assignements is dependent on the control input:

module mytest(

input logic control,

input real inA,

input real inB,

output real myOut[5:0]

);

assign myOut[5:0] = ( control == 1'b1) ? {inA, inA, inA, inB, inB) : {inB, inA, inB, inA, inB} ;

But this does not work, since it does not accept the array {} for the assignement.

How can I do this assignement properly ?

Parents

  • You are trying to do concatenation when what you want to do is array assignment. Also, your array was too big for the assignment. Here is the code that works:

    module mytest(
      input logic control,
      input real inA,
      input real inB,
      output real myOut[4:0]
    );

      assign myOut[4:0] = ( control == 1'b1) ? '{inA, inA, inA, inB, inB} : '{inB, inA, inB, inA, inB} ;

    endmodule

    Tim

  • in reply to tpylant

    Hi Tim,

    yes, the example was buggy as the dimensions of the arrays did not match. Thanks for the working example. 

    Is there a way to write the array in a short form - assume I do have a 64-bit array and want to assign all "inA" or "inB".

    Can I do something like this:

    assign myOut [63:0] = ( control == 1'b1) ? [63:0] inA : [63:0] inB;

    I want to avoid to type 64-time the "inA" / "inB"  in brackets, like '{inA, inA, inA ...}.

  • in reply to HoWei

    You should look up "SystemVerilog array assignment" to confirm, but I think the following will work:

    assign myOut[64] = (control==1'b1) ? '{ 64 {inA} } : '{ 64 {inB} };

    Tim

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